/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __PHY2_NX_USB_REG_H__
#define __PHY2_NX_USB_REG_H__

#include <linux/types.h>

/* registers offset */
#define USBCTRL					0x00
#define USBDBG					0x08
#define PHYCFG					0x10
#define PHYTEST					0x14
#define PHYTUNE					0x18
#define USBPHYDBG				0x1C
#define USBCOMCFG				0x20
#define PHYSTAT					0x2C

/* USB Control Register */
typedef union {
	u32 val;
	struct {
	u32 mode:2;
	u32 wakeup:2;
	u32 rsvd0:3;
	u32 sus_valid:1;
	u32 susp:1;
	u32 susp_signal:1;
	u32 susp_sel:1;
	u32 rsvd1:5;
	u32 lscd_en:1;
	u32 lscd_flg:1;
	u32 lsci_en:1;
	u32 rsvd2:2;
	u32 dma_check_hwend:1;
#if IS_ENABLED(CONFIG_ARCH_LOMBO_N7V7)
	u32 rsvd3:6;
	u32 sim_spdup:1;
	u32 susp_sof_fixed:1;
	u32 rsvd4:2;
#else
	u32 rsvd3:10;
#endif
	} bits;
} reg_usb_usbctrl_t;

#define USB_USBCTRL_SUS_VALID_1			0x1
#define USB_USBCTRL_SUS_VALID_0			0x0
#define USB_USBCTRL_SUSP_1			0x1
#define USB_USBCTRL_SUSP_0			0x0
#define USB_USBCTRL_SUSP_SIGNAL_1		0x1
#define USB_USBCTRL_SUSP_SIGNAL_0		0x0
#define USB_USBCTRL_SUSP_SEL_1			0x1
#define USB_USBCTRL_SUSP_SEL_0			0x0
#define USB_USBCTRL_DMA_CHECK_HWEND_0		0x0
#define USB_USBCTRL_DMA_CHECK_HWEND_1		0x1

/* USB Debug Register */
typedef union {
	u32 val;
	struct {
	u32 f_id:2;
	u32 f_avalid:2;
	u32 f_bvalid:2;
	u32 f_vbusv:2;
	u32 f_sess:2;
	u32 rsvd0:22;
	} bits;
} reg_usb_usbdbg_t;

#define USB_USBDBG_F_ID_0			0x0
#define USB_USBDBG_F_ID_1			0x1
#define USB_USBDBG_F_ID_2			0x2
#define USB_USBDBG_F_ID_3			0x3
#define USB_USBDBG_F_AVALID_0			0x0
#define USB_USBDBG_F_AVALID_1			0x1
#define USB_USBDBG_F_AVALID_2			0x2
#define USB_USBDBG_F_AVALID_3			0x3
#define USB_USBDBG_F_BVALID_0			0x0
#define USB_USBDBG_F_BVALID_1			0x1
#define USB_USBDBG_F_BVALID_2			0x2
#define USB_USBDBG_F_BVALID_3			0x3
#define USB_USBDBG_F_VBUSV_0			0x0
#define USB_USBDBG_F_VBUSV_1			0x1
#define USB_USBDBG_F_VBUSV_2			0x2
#define USB_USBDBG_F_VBUSV_3			0x3
#define USB_USBDBG_F_SESS_0			0x0
#define USB_USBDBG_F_SESS_1			0x1
#define USB_USBDBG_F_SESS_2			0x2
#define USB_USBDBG_F_SESS_3			0x3

/* USB PHY Config Register */
typedef union {
	u32 val;
	struct {
	u32 prpu_sel:2;
	u32 ldo3318_lpn_manual:1;
	u32 ldo3318_lpn_ctrl:1;
	u32 hsdatamux_sel:2;
	u32 ef_ctrl:1;
	u32 ef_bypass:1;
	u32 ed_type:1;
	u32 clk480m_edge:1;
	u32 cdrrstn_sel:2;
	u32 cdrrstn:1;
	u32 cdrdebug_sel:1;
	u32 cdrdebug_en:1;
	u32 analb_txen:1;
	u32 analb_rxen:1;
	u32 analb_tx_forcese0:1;
	u32 rxprbs7sche_en:1;
	u32 resusb20_sel:7;
	u32 resusb20_en:1;
	u32 nsqfilt_sel:1;
	u32 rsvd0:4;
	} bits;
} reg_usb_phycfg_t;

#define USB_PHYCFG_LDO3318_LPN_MANUAL_0		0x0
#define USB_PHYCFG_LDO3318_LPN_MANUAL_1		0x1
#define USB_PHYCFG_LDO3318_LPN_CTRL_0		0x0
#define USB_PHYCFG_LDO3318_LPN_CTRL_1		0x1

/* USB PHY Test Register */
typedef union {
	u32 val;
	struct {
	u32 cfg_datain:8;
	u32 cfg_addr:4;
	u32 cfg_clk:1;
	u32 bist_start:1;
	u32 bist_ls_en:1;
	u32 bist_fs_en:1;
	u32 bist_hs_en:1;
	u32 bist_sel:1;
	u32 rsvd0:14;
	} bits;
} reg_usb_phytest_t;

/* USB PHY Tune Register */
typedef union {
	u32 val;
	struct {
	u32 txvreftune:4;
	u32 txrisetune:2;
	u32 txrestune:2;
	u32 txpreempulsetune:1;
	u32 txpreempamptune:2;
	u32 hsxvtune:2;
	u32 fslstune:4;
	u32 sqrxtune:3;
	u32 discontune:3;
	u32 rsvd0:9;
	} bits;
} reg_usb_phytune_t;

/* USB PHY Debug Register */
typedef union {
	u32 val;
	struct {
	u32 rsvd0:16;
	u32 vatest_xcvr:1;
	u32 comp_sel_analog:1;
	u32 sqrx_test:5;
	u32 tx_test:3;
	u32 comp_test:1;
	u32 sliver_override_en:1;
	u32 sliver_override:4;
	} bits;
} reg_usb_usbphydbg_t;

/* USB Common Config Register */
typedef union {
	u32 val;
	struct {
	u32 vatest_common:1;
	u32 pll_vref_sel:2;
	u32 pll_res_sel:2;
	u32 pll_kvco_sel:3;
	u32 pll_icp_sel:2;
	u32 clk12m_s:1;
	u32 reg_bias_test:1;
	u32 bias_test:2;
	u32 pll_test:5;
	u32 xo_pu:1;
	u32 rsvd0:12;
	} bits;
} reg_usb_usbcomcfg_t;

/* USB PHY Status Register */
typedef union {
	u32 val;
	struct {
	u32 testdatout:4;
	u32 rsvd0:28;
	} bits;
} reg_usb_phystat_t;

#endif /* __PHY2_NX_USB_REG_H__ */
